I/O map

AddressR/WDescription
00h
F
0Eh
R Keyboard matrix

_ D0 D1 D2 D3 D4 D5 D6 D7
00h 0 1 2 3 4 5 6 7
01h 8 9 * + = D C RETURN
02h @ A B C D E F G
03h H I J K L M N O
04h P Q R S T U V W
05h X Y Z [ (\) ] ^ -
06h 0 1 2 3 4 5 6 7
07h 8 9 F G C D / Q
08h HOME
CLR
INS
DEL
GRPH Ji (Kana) SHIFT CTRL
09h STOP f.1 f.2 f.3 f.4 f.5 SPACE ESC
0Ah HTAB HELP COPY - / CAPS
LOCK
0Bh ROLL
UP
ROLL
DOWN






0Ch f.6 f.7 f.8 f.9 f.10 BS INS DEL
0Dh ϊ (Conversion) (Decision) PC Sp (Full-width)



0Eh RETURN
(Main)
RETURN
(Numeric keypad)
SHIFT
(Left)
SHIFT
(Right)



(0)

Colored cells are numeric keypad keys.
Always 0 for keyboards after FH

Keys from 0Ch to 0Eh are only available on FH and later keyboards.
10hW Printer data output and calendar clock (PD1990AC) output

Bit76543210
SignalPrinter data output

Bit76543210
Signal
CDOC2C1C0

C2, C1, C0Command output to PD1990AC
CDOData output to PD1990AC
20hR/W USART (PD8251C) data port
21hR/W USART (PD8251C) control port
AddressR/WDescription
30hW System control port

Bit76543210
Signal
BS MTON CDS COLOR 40

BS USART channel control 00: CMT 600 baud
01: CMT 1200 baud
10: RS-232C
11: RS-232C
MTON Motor control 0: Motor OFF
1: Motor ON
CDS Carrier control 0: Space (1200 Hz)
1: Mark (2400 Hz)
COLOR Text screen color mode 0: Color mode
1: Black and white mode
40 Columns mode 0: 40 columns mode
1: 80 columns mode
R Mode select (dip switch status)

Bit76543210
Signal
SW1-S5 SW1-S4 SW1-S3 SW1-S2 SW1-S1 SW4-S1

SW1-S5 When receiving DEL code 0: Process
1: Ignore
SW1-S4 S-parameter 0: Enabled
1: Disabled
SW1-S3 Number of text lines 0: 25 lines
1: 20 lines
SW1-S2 Number of text columns 0: 80 columns
1: 40 columns
SW1-S1 Startup mode 0: Terminal mode
1: BASIC mode
SW4-S1 BASIC mode 0: N-BASIC
1: N88-BASIC
31hW System control port

Bit76543210
Signal
25LINE HCOLOR GRAPH RMODE MMODE 200LINE

25LINE High resolution CRT 25 lines mode control 0: All modes except high resolution CRT 25 lines mode
1: High resolution CRT 25 lines mode
HCOLOR Graphics screen color mode 0: Black and white mode
1: Color mode
GRAPH Graphics control 0: Do not display the graphics screen
1: Display graphics screen
RMODE ROM mode 0: N88-BASIC mode
1: N-BASIC mode
MMODE RAM mode 0: ROM/RAM mode
1: 64K RAM mode
200LINE Graphics control in high resolution CRT mode 0: 640~400 dots mode
1: 640~200 dots mode
R Mode select (dip switch status)

Bit76543210
Signal SW4-S2 SW3-S0 SW2-S6 SW2-S5 SW2-S4 SW2-S3 SW2-S2 SW2-S1

SW4-S2 V1/V2 mode 0: V2 mode
1: V1 mode
SW3-S0 High speed mode 0: Standard mode (V1S)
1: High speed mode (V1H, V2)
SW2-S6 Communication method 0: Half duplex
1: Full duplex
SW2-S5 X-parameter 0: Enabled
1: Disabled
SW2-S4 Stop bit length 0: 2 bits
1: 1 bit
SW2-S3 Data bit length 0: 8 bits
1: 7 bits
SW2-S2 Parity polarity 0: Even number
1: Odd number
SW2-S1 Parity check 0: With parity
1: No parity
32hR/W Mode specification (Since it is not present in PC-8801mkII or earlier, please check SR or later before accessing)

Bit76543210
Signal SINTM GVAM PMODE TMODE AVC EROMSL

SINTM Sound interrupt mask 0: Enable sound interrupts
1: Disable sound interrupts
GVAM Graphics VRAM access mode 0: Independent access mode
1: Extended access mode
PMODE Palette mode 0: Digital 8 colors mode
1: Analog 512 colors mode
TMODE Fast RAM access mode
(Only valid in V1H, V2 mode)
0: F000h to FFFFh access high-speed RAM
1: F000h to FFFFh access main RAM
AVC Screen output mode 00: TV/Video Out
01: (Prohibited)
10: Computer output
11: Option mode
EROMSL Built-in expansion ROM bank selection
(4th ROM)
00: Bank 0
01: Bank 1
10: Bank 2
11: Bank 3
34hW Extended access mode ALU control

Bit76543210
Signal
ALU21 ALU11 ALU01
ALU20 ALU10 ALU00

ALU01:ALU00
ALU11:ALU10
ALU21:ALU20
Graphics ALU mode (GVRAM0)
Graphics ALU mode (GVRAM1)
Graphics ALU mode (GVRAM2)
00: Bit reset
01: Bit set
10: Bit inversion
11: No operation
35hW Extended access mode GVRAM control

Bit76543210
Signal GAM
GDM
PLN2 PLN1 PLN0

GAM GVRAM access mode 0: Main RAM access
1: GVRAM access
GDM Graphics data multiplexer control 00: Write ALU output data to 3 planes simultaneously
01: Write data / Read in the previous read cycle to 3 planes simultaneously
10: Write the GVRAM1 data / Read in the previous read cycle to GVRAM0.
11: Write the GVRAM0 data / Read in the previous read cycle to GVRAM1.
PLN2 GVRAM2 comparison data
PLN1 GVRAM1 comparison data
PLN0 GVRAM0 comparison data
AddressR/WDescription
40hW Strobe port

Bit76543210
Signal FBEEP JOP1 BEEP GHSM CLDS CCK CSTB PSTB

FBEEP Sound output Output port waveform as audio
JOP1 General purpose output port Joystick port output (pin 8)
BEEP BEEP sound control 0: BEEP OFF
1: BEEP ON
GHSM Graphics high speed mode
(Only valid in V1S mode)
0: Standard mode
1: High speed mode
CLDS CRT I/F synchronous control 0: Synchronization bit OFF
1: Synchronization bit ON
CCK Shift clock for calendar clock 0: Clock OFF
1: Clock ON
CSTB Calendar clock strobe 0: Strobe OFF
1: Strobe ON
PSTB Printer strobe 0: Strobe ON
1: Strobe OFF
R System mode sense

Bit76543210
Signal
VRTC CDI SW2-S7 DCD SHG BUSY

VRTC Vertical retrace signal from CRTC (PD3301AC) 0: Vertical display period
1: Vertical retrace period
CDI Data from calendar clock (PD1990AC)
SW2-S7 Disk boot mode 0: Boot from disk
1: Do not boot from disk
DCD RS-232C data carrier detection 0: Carrier OFF
1: Carrier ON
SHG High resolution CRT mode 0: High resolution CRT mode (24 kHz)
1: Standard CRT mode (15kHz)
BUSY Printer BUSY 0: Ready
1: Busy
44hR/W FM sound control

Before FR/MR: OPN
FH/MH and later: OPNA SSG/FM1-3
45hR/W FM sound data

Before FR/MR: OPN
FH/MH and later: OPNA SSG/FM1-3
46hR/W FM sound control

FH/MH and later only: OPNA ADPCM/FM4-6
47hR/W FM sound data

FH/MH and later only: OPNA ADPCM/FM4-6
AddressR/WDescription
50hR/W CRTC (PD3301AC) control port
51hR/W CRTC (PD3301AC) control port
52hW Background color control (8-color digital RGB)

Bit76543210
Signal
BGGRB

BGGRB Specify background color
53hW Screen display control

Bit76543210
Signal
G2DS G1DS G0DS TEXTDS

G2DS GVRAM2 display 0: Displayed
1: Hidden
G1DS GVRAM1 display 0: Displayed
1: Hidden
G0DS GVRAM0 display 0: Displayed
1: Hidden
TEXTDS Text screen display 0: Displayed
1: Hidden

Set G2DS to 1 in 640~400 dot mode.
In color graphics mode, the graphics screen is displayed regardless of GxDS settings
54h
F
5Bh
W Palette
  • 8 colors mode
    Bit76543210
    Signal
    PGRB

    PGRB Specify color

  • 512 colors mode
    Bit76543210
    Signal 00PR2PR1PR0PB2PB1PB0
    01
    PG2PG1PG0
    10BR2BR1BR0BB2BB1BB0
    11
    BG2BG1BG0

    PR[2:0] Red level
    PB[2:0] Blue level
    PG[2:0] Green level
    BR[2:0] Background color red level
    BB[2:0] Background color blue level
    BG[2:0] Background color green level
5ChW GVRAM independent access mode bank selection
GVRAM0 (blue plane) selection
R GVRAM bank status

Bit76543210
Signal
G2 G1 G0

G2 GVRAM2 status 0: Not selected
1: Selected
G1 GVRAM1 status 0: Not selected
1: Selected
G0 GVRAM0 status 0: Not selected
1: Selected
5DhW GVRAM independent access mode bank selection
GVRAM1 (red plane) selection
5EhW GVRAM independent access mode bank selection
GVRAM2 (green plane) selection
5FhW GVRAM independent access mode bank selection
Main RAM selection
AddressR/WDescription
60h
F
68h
R/W DMAC (PD8257C-5) control/status port
6EhR CPU clock mode

Bit76543210
Signal 8 MHz/4 MHz

8 MHz/4 MHz CPU clock mode 0: 8 MHz
1: 4 MHz
6FhR/W RS-232C baud rate (FH or later)

Bit76543210
Signal
BR

BRBaud rate
000075
0001150
0010300
0011600
01001200
01012400
01104800
01119600
100019200
1001`1111Invalid
70hR/W Text window offset address.
Upper 8 bits of text window offset address.
71hR/W Expansion ROM selection

Bit76543210
Signal EROM7 EROM6 EROM5 EROM4 EROM3 EROM2 EROM1 IEROM

EROM7 Expansion ROM7 Selection 0: Selected
1: Not selected
EROM6 Expansion ROM6 selection 0: Selected
1: Not selected
EROM5 Expansion ROM5 selection 0: Selected
1: Not selected
EROM4 Expansion ROM4 selection 0: Selected
1: Not selected
EROM3 Expansion ROM3 selection 0: Selected
1: Not selected
EROM2 Expansion ROM2 selection 0: Selected
1: Not selected
EROM1 Expansion ROM1 selection 0: Selected
1: Not selected
IEROM Expansion ROM0 selection (4th ROM) 0: Selected
1: Not selected

Do not set multiple bits to 0 at the same time
When all bits are 1, main ROM is selected.
78hW Increment text window offset address by 1
AddressR/WDescription
A8hR/W FM sound source control (Soundboard II)
OPNA SSG/FM1-3
A9hR/W FM sound source data (Soundboard II)
OPNA SSG/FM1-3
AAhW Soundboard II interrupt mask

Bit76543210
Signal S2INTM

S2INTM Soundboard II interrupt mask 0: Enable sound interrupts
1: Disable sound interrupts
AChR/W FM sound source control (Soundboard II)
OPNA ADPCM/FM4-6
ADhR/W FM sound source data (Soundboard II)
OPNA ADPCM/FM4-6
AddressR/WDescription
E2hW Expanded RAM read/write control

Bit76543210
Signal
WREN
RDEN

WREN Extended RAM write control 0: Cannot be written
1: Writable (write accesses from 0000h to 7FFFh are performed to expanded RAM)
RDEN Extended RAM read control 0: Cannot be read
1: Readable (read accesses from 0000h to 7FFFh are performed to expansion RAM)
R Expansion RAM read/write control status

Bit76543210
Signal
WREN
RDEN

WREN Extended RAM write control status 0: Writable
1: Cannot be written
RDEN Extended RAM read control status 0: Readable
1: Cannot be read
E3hR/W Expansion RAM bank selection

Bit76543210
Signal
CARD BANK

CARD Card number 00: Card 0 (M series expansion 128 KB RAM)
01: Card 1
10: Card 2
11: Card 3
BANK Bank number 00: Bank 0
01: Bank 1
10: Bank 2
11: Bank 3
E4hW Interrupt level setting

Bit76543210
Signal
SGS B2 B1 B0

SGS Control of status register 0: Interrupt compared to interrupt level
1: Interrupt by priority
B[2:0] Setting the interrupt level
Interrupt levelInterrupt source
0 (Highest)RS-232C reception interrupt
1VRTC interrupt
21/600 second timer interrupt
3INT4
4Sound interrupt
5INT2
6FDINT1
7 (Lowest)FDINT2

Example: If you set E4h to 03h, interrupts of level 3 or lower (3 to 7) will not occur.
E6hW Interrupt mask

Bit76543210
Signal
RXMF VRMF RTMF

RXMF USART (RS-232C) reception interrupt mask 0: Disabled
1: Enabled
VRMF VRTC interrupt mask 0: Disabled
1: Enabled
RTMF 1/600 second timer interrupt mask 0: Disabled
1: Enabled
E8hW Set Kanji ROM address lower 8 bits.
R Read the right 8 bits of the Kanji ROM font (even lines for half-width and quarter-width characters).
E9hW Set Kanji ROM address upper 8 bits.
R Read the left 8 bits of the Kanji ROM font (odd lines for half-width and quarter-width characters).
EAhW Start reading Kanji ROM.
EBhW End reading Kanji ROM.
EChW Set second level kanji ROM address lower 8 bits.
R Read the right 8 bits of the second level Kanji ROM font.
EDhW Set second level kanji ROM address upper 8 bits.
R Read the left 8 bits of the second level Kanji ROM font.
AddressR/WDescription
FChR/W Disk subsystem I/F 8255 port A
In the standard state, it is a data reception port from the subsystem.
FDhR/W Disk subsystem I/F 8255 port B
In the standard state, it is a data transmission port to the subsystem.
FEhR/W Disk subsystem I/F 8255 port C

Bit76543210
R/WWR
Signal ATN DAC RFD DAV
DAC RFD DAV

ATN W Attention Set to 1 when sending a command to the subsystem or to interrupt a command
DAC Data Accepted Set to 1 after fetching data from the subsystem
RFD Ready For Data Set to 1 when requesting data from the subsystem
DAV Data Valid Set to 1 after outputting data to port B
DAC R Data Accepted Becomes 1 after the subsystem picks up data
RFD Ready For Data Becomes 1 when the subsystem requests data
DAV Data Valid Becomes 1 after data is output to port A
FFhW Disk subsystem I/F 8255 control

Joystick (SR and later)

Read through SSG I/O ports A and B.
The common output (pin 8) is operated by Bit 6 of I/O port 40h.

SSG registerR/WDescription
07hW I/O port A, B input/output settings

Bit76543210
Signal IOB IOA Noise Tone

IOB I/O port B input/output 0: Input
1: Output
IOB I/O port A input/output 0: Input
1: Output

When using a joystick, set both ports to input.
0EhR I/O port A

Bit76543210
Signal
RIGHT LEFT DOWN UP
0FhR I/O port B

Bit76543210
Signal
TRG2 TRG1